Complementary MOS integrated circuits having vertical channel FETs

ABSTRACT

A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET&#39;s have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.

DESCRIPTION

1. Technical Field

The present invention relates to semiconductor integrated circuits, andparticularly to semiconductor integrated circuits (C-MOS circuits:complementary MOS circuits) having a p-channel FET (field-effecttransistor) and an n-channel FET.

2. Background Art

A semiconductor integrated circuit having an n-channel FET and ap-channel FET can be represented by a CMOS integrated circuit employinginsulated gate-type field-effect transistors (MOS transistors) as FET's.

The CMOS integrated circuit is fundamentally based upon an invertercircuit which consists of an n-channel MOS transistor 1 and a p-channelMOS transistor 2 as shown in FIG. 1, wherein reference numeral 3 denotesan input terminal, 4 denotes an output terminal, 5 denotes a Vssterminal, and 6 denotes a Vcc terminal.

Referring to FIG. 2, the inverter circuit of FIG. 1 consists of then-channel MOS transistor 1 and the p-channel MOS transistor 2 formed ina p-type well region 9 and an n-type well region 11, that are formed ina silicon substrate 10. Here, though both the p-type well region and then-type well region are formed, the silicon substrate 10 may be utilizedto serve as either one of them, so that only either one well regionneeds be formed. In FIG. 2, the n-type well region and the p-type wellregion are formed in the n⁻ -type well region. In FIG. 2, furthermore,reference numeral 7 denotes n⁺ -type regions, 8 denotes p⁺ -typeregions, 12 denotes field insulators for device isolation, 13 denotesgate electrodes, 14 denotes insulators, 90 denotes p-type regions, and91 denotes n-type regions.

The CMOS structure has heretofore been formed in plane as shown in FIG.2. That is, a wide field oxide film 12 must be formed in order toelectrically isolate the n-channel MOS transistor 1 from the p-channelMOS transistor 2. Further, the p-type well region and the n-type wellregion must be separated from each other when there arises a problem ofbreakdown voltage therebetween due to their high impurityconcentrations. In either case, the CMOS device is prevented from beingintegrated to a high degree. In the integrated circuit having a 2μm-long gate level, for instance, the field oxide film 12 must have awidth of about 10 μm to isolate the wells. Even in the integratedcircuit having a 1 μm-long gate level, the field oxide film must have awidth of about 5 μm.

The above-mentioned known C-MOS technique has been disclosed in JapanesePatent Publication Nos. 44555/1974 and 33229/1974.

DISCLOSURE OF INVENTION

Further, so-called vertical MOSFET's and V-grooved MOSFET's havingresembling appearance or construction have been disclosed in JapanesePatent Publication Nos. 26823/1968 and 456/1968.

DISCLOSURE OF THE INVENTION

The object of the present invention is to provide well-to-well isolationof a high-density structure that had been one of the greatest obstaclesagainst realizing the semiconductor integrated circuits of the CMOSconstruction in a highly integrated form.

According to the present invention, the skeltal structure resides inthat a p-well (n-channel forming region) and an n-well (p-channelforming region) are formed being opposed to each other with a thininsulating region interposed therebetween, in order to realize a CMOSintegrated circuit in a highly integrated form.

According to the present invention, an n-channel MOS transistor isisolated from a p-channel MOS transistor by a thin insulating region,making it possible to obtain the CMOS integrated circuit in a highlyintegrated form and to very efficiently prevent the occurrence of alatch-up that is detrimental to the CMOS construction. Moreover, it isallowed to form transistors having a particularly large transferconductance in very small regions.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram of a conventional CMOS inverter;

FIG. 2 is a section view showing the structure of a conventional CMOSinverter;

FIGS. 3, 4, 5 and 6 are section views showing the manufacturing stepsaccording to an embodiment of the present invention;

FIG. 7 is a bird's -eye view showing a first embodiment of the presentinvention;

FIG. 8 is a section view of a substrate employed for a second embodimentof the present invention;

FIG. 9 is a section view showing the second embodiment of the presentinvention;

FIG. 10 is a section view of a substrate employed for a third embodimentof the present invention;

FIG. 11 is a section view showing the third embodiment of the presentinvention;

FIG. 12 is a section view showing a fourth embodiment according to thepresent invention;

FIG. 13 is a bird's-eye view showing a fifth embodiment according to thepresent invention; and

FIG. 14 is a bird's -eye view showing a sixth embodiment according tothe present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment of FIGS. 3 to 7:

A first embodiment of the present invention is shown in FIGS. 3 to 7,wherein the same reference numerals denote the same or equivalentportions. According to the first embodiment of the present invention,protruding poles 18 and 19 are formed on a silicon substrate 10. Asshown in FIG. 3, an n⁺ -type region 15 and a p⁺ -type region 16 havingan impurity concentration of greater than 10²⁰ cm⁻³ are formed in then-type silicon substrate 10 (about 1 to 100 ohms-cm, and a concentrationof 1×10¹⁴ 1×10¹⁷ cm⁻³ ) by the customarily employed ion implantationmethod or the thermal diffusion method. The n³⁰ -type region 15 has adepth of about 0.2 to 1 μm, and the p⁺ -type region has a depth of about0.4 to 1.5 μm. Since the silicon substrate 10 of the n-type type isemployed, the lower periphery of the n⁺ -type region 15 is wrapped by ap-type well region 9 which is formed to have a depth of about 1 to 5 μm.If the p-type well region 9 is formed being self-aligned using a maskfor forming the n⁺ -type region 15, no extra region is needed for maskalignment, and the elements can be formed highly densely. Even when thesame mask is used, the p-type well region 9 is so formed as to wrap then⁺ -type region 15 owing to the diffusion of impurities. Further, an n⁻-type or a p⁻ -type epitaxial layer 17 is grown to have a thickness ofabout 0.5 to 2 μm. Then, as shown in FIG. 4, the protruding poles 18, 19are formed by dry etching, and p-type dopants and n-type dopants areimplanted thereinto, respectively, so that they cancel or add up to theimpurities that have been added already in the epitaxial layer 17 toaccomplish an impurity concentration over a range of 10¹⁴ to 10¹⁷ cm⁻³as desired. Thus, the p-type protruding pole 18 and the n-typeprotruding pole 19 are formed.

When the dry etching or the ion implantation is to be effected, it is ofcourse allowable to use, as a so-called mask, an anti-etching film or ananti-ion implantation film of any desired shape relying upon the widelyknown photolithography.

Then, an isolation-insulator 20 is formed between the two protrudingpoles by the thermal oxide or the chemical vapor deposition. Theisolation-insulator 20 has a thickness of about 0.1 to 1 μm between thep-type region 18 and the n-type region 19. When the chemical vapordeposition method is used, the insulator 20 is uniformly depositedaround the protruding poles, and the gap between the protruding poles 18and 19 is filled with it. Then, the whole protruding poles 18 and 19 aresubjected to the solution etching or dry etching to remove the insulator20 except from the gap as shown in FIG. 4.

When the thermal oxide film is to be formed, the oxide film grows fromboth the protruding poles 18 and 19; the thermal oxidation isdiscontinued when the oxide has met with each other from both sides.Then, the isotropic etching is effected to remove the whole oxide filmin a manner to peel it off.

The oxide film 20 is protected by the protruding poles 18, 19 and is notsubjected to the etching. Therefore, the structure shown in FIG. 4 isobtained.

Then, as shown in FIG. 5, a field oxide film 12 is formed to have athickness of 200 to 1000 nm on the isolation region by the localoxidation of silicon or the like and a gate oxide film 21 is formed bythe thermal oxidation method to have a thickness of 5 to 100 nm. In thiscase, an anti-oxidation film such as silicon nitride (Si₃ N₄) film orthe like is formed on the areas except the portion where the field oxidefilm 12 is formed, and is oxidized.

Thereafter, polycrystalline silicon, a refractory metal, or a silicidethereof is deposited on the whole surface thereof by the sputteringmethod or the chemical vapor deposition method. The whole surface issubjected to the dry etching of a strong directivity while leaving aresist resin for dry etching on the wiring portions. Then, the film lefton the side walls of the protruding pcles 18, 19 serve as a gate 13. Thefilm that serves as the gate 13 has a thickness of about 0.1 to 0.8 μm.An n₃₀ -type region 151 and a p⁺ -type region 161 are then formed by theion implantation, diffusion or the like to have a depth of about 0.1 to0.5 μm. Then, as shown in FIG. 6, an intermediate insulator 22 asrepresented by the CVD·PSG is deposited to have a thickness of 0.5 to1.0 μm, a connection hole 24 is formed in a desired portion, andelectrodes 231 to 233 as represented by aluminum are formed. Theelectrodes 231, 232 and 233 serve as Vss terminal, output terminal, andVcc terminal, respectively.

FIG. 7 is a birds-eye view showing, in cross section, the structure ofthe embodiment of FIG. 5. A flat portion 131 of the gate 13 is used forconnection to the wiring or the electrode.

Embodiment of FIGS. 8 and 9:

According to a second embodiment of the present invention, when the sameelements as those of the first embodiment are to be formed on theinsulating substrate, the n⁺ -type region 15 needs not be electricallyisolated from the substrate 10. Therefore, the degree of integration canbe further increased.

That is, as shown in FIG. 8, a thin silicon substrate layer 101 isformed on the whole surface of a sapphire or a single crystalline spinelsubstrate 25, and the n⁺ -type region 15 and the p⁺ -type region 16 areformed in the layer 101. Thereafter, the structure shown in FIG. 9 isobtained through the same steps as those explained with reference toFIGS. 4 to 6. The n⁺ -type region 15 and the p⁺ -type region 16 arecompletely isolated by the insulator 20 and the insulating substrate 25.Therefore, there is no need of forming the p-type well 9, and the mutualinterference effect can be minimized.

In FIG. 9, furthermore, thickness of the field oxide film 12 can beincreased until it penetrates through the silicon substrate 101, makingit possible to establish more complete isolation from other elements.

The insulator 20 should reach the insulating substrate 25 so as toisolate the silicon substrate 101.

Therefore, when the insulator 20 is to be formed by the chemical vapordeposition, the silicon substrate 101 must be etched prior to depositingthe insulator.

Embodiment of FIGS. 10 and 11:

According to a third embodiment of the present invention as shown inFIG. 10, the insulating substrate is comprised of an insulating-filmsubstrate 25 such as of thermal oxide, a sapphire or spinel formed onthe silicon substrate 10, and an SOI(silicon on insulator)-Si substrate102 formed by the liquid-phase lateral epitaxial growth method from aseeded region 26 where the silicon substrate 10 is exposed by using thelaser or a strip heater. The SOI-single crystalline silicon substrate102 can be formed without using the seeded region 26. Generally,however, the crystalline substrate 102 of good quality can be formedwhen the seeded region is used.

Thereafter, an integrated circuit of FIG. 11 is formed in the samemanner as the above-mentioned embodiment of FIG. 9. The seeded region 26is not shown in FIG. 11.

According to this embodiment employing the silicon substrate 10, it isallowable to form resistors and capacitors in the substrate to use themin combination with the CMOS transistor of the present invention formedthereon via the insulating film 25. It is further allowable to form anMOS transistor on the surface of the silicon substrate 10 and to formthe CMOS transistor of the present invention thereon via the insulatingfilm 25 in two-layer construction, in order to enhance the functions andto increase the degree of integration.

Embodiment of FIG. 12:

In the embodiment of FIG. 11, both the n⁺ -type region 15 and the p⁺-type region 16 are formed in the SOI-Si substrate layer 102. However,either one of them may be formed in the seeded region 26 as shown inFIG. 12. This enables the one region (n⁺ -type region in FIG. 12) to beconnected to the silicon substrate 10, presenting great advantage.

In the fourth embodiment of the present invention, an n-type protrudingportion 19 and a p-type protruding portion 18 correspond to the n-typewell and the p-type well of the CMOS transistor, respectively. Thesewells are isolated by the isolation-insulator 20 having a thickness of0.1 to 1 μm, which is much smaller than the width of the isolationregion of the the conventional CMOS construction shown in FIG. 2 thatranges as great as 5 to 10 μm.

Embodiment of FIG. 13:

In the aforementioned embodiments of the present invention, theisolation region is filled with the insulator 20. However, this regionmay be packed with a thermally oxidized film SiO₂ and crystallinesilicon. According to the present invention, the whole region 20 shouldwork as an insulation region, and no limitation is imposed on thematerial constituting the insulation region.

FIG. 13 shows a fifth embodiment of the present invention. In this case,the isolation-insulator 20 of the embodiment of FIG. 6 is substituted bythe combination of a gate oxide film 21 and a gate 13. Side surfaces ofthe protruding silicon poles 18, 19 are all surrounded by the gate oxidefilm 21, and the region between the two protruding poles is packed withthe gate 13. In this case, the whole side surfaces of the protrudingpoles 18, 19 serve as a channel of the transistor. Therefore, atransistor having a large transfer conductance is obtained in a verysmall region.

In the embodiment of FIG. 6, only the interface between the protrudingpole 18 and the insulating film 21 serves as the channel. In the fifthembodiment, however, the channel can be formed even on the surfaceopposed to the abovesaid channel of the protruding pole 18, since thegate 13 exists in the insulator 20.

The n⁺ -type region 15 must be extended up to the channel-formingregion. Concretely speaking, the device should be constructed as shownin FIGS. 9, 11 and 12.

Similarly, the channel can be formed along the whole peripheral surfaceof the protruding pole 18.

The same also holds true even for the protruding pole 19.

Embodiment of FIG. 14:

FIG. 14 illustrates a sixth embodiment of the present invention.

In the aforementioned embodiments of the present invention, the p-typeand n-type protruding poles 18, 19 had been independently provided. Inthe sixth embodiment, however, a plurality of p-type protruding polesand a plurality of n-type protruding poles are formed contiguous to eachother in the form of beams. To isolate from the neighboring CMOSinverters, thick field oxide films 12 are formed at desired portions.The gate oxide films 21 are formed on the side surfaces the protrudingbeams, and the gate 13 is formed across the beams. FIG. 14 shows thecase where two CMOS inverters are formed.

In the aforementioned embodiments, the p-type well region 9 had beenprovided necessarily. The p-type well region 9, however, may not beformed provided the substrate 10 has a high resistance. In this case,the substrate should have a resistance of greater than 100 ohms-cm, andpreferably about one kiloohms-cm.

The substrate will have an impurity concentration of from 1×10¹³ to1×10⁻ cm⁻³.

Industrial Applicability

In the conventional CMOS transistor formed on the silicon substrate, then-channel transistor and the p-channel transistor interfered with eachother giving rise to the occurrence of a so-called latch-up, whichcaused the integration circuit to become inoperative or broken down.

The CMOS transistors are now being regarded as the main transistors inthe MOS-type integrated circuits that occupy a majority proportion ofthe semiconductor industries. However, the latch-up is one of the greatfactors that hinders the CMOS integrated circuits from being integratedhighly densely, depriving the CMOS transistors of their merits to aconsiderable degree.

According to the present invention, not only the above defect inherentin the CMOS transistor is removed but also the channel is formed in thevertical direction, making it possible to provide a large currentdriving ability with a very small plane area. Therefore, the presentinvention is adapted to further increasing the density of integrationand can be applied to general CMOS integrated circuits. Namely, thepresent invention provides the technique for increasing the integrationdensity that can be applied to most of the MOS integrated circuits, andoffers very great industrial values.

What is claimed is:
 1. A semiconductor integrated circuit comprising:asubstrate having a semiconductor layer on at least a first main surfacethereof; a first region of a first type of conductivity formed in saidsemiconductor layer; a second region of a second type of conductivityformed in said semiconductor layer; a first semiconductor protruding apole-like region of the second type of conductivity that is so providedas to come into contact, with at least a portion thereof, with saidfirst region, and a second semiconductor protruding pole-like region ofthe first type of conductivity that is so provided as to come intocontact, with at least a portion thereof, with said second region,wherein said first and second protruding pole-like regions are providedas a mesa; a first isolation region provided between said firstsemiconductor protruding pole-like region and said second semiconductorprotruding pole-like region; a third region of the first type ofconductivity provided in said first semiconductor protruding pole-likeregion; a fourth region of the second type of conductivity provided insaid second semiconductor protruding pole-like region; a first gateelectrode formed on said first semiconductor protruding pole-like regionvia a first gate insulating film opposite to the first isolation region;and a second gate electrode formed on said second semiconductorprotruding pole-like region via a second gate insulating film oppositeto the first isolation region.
 2. A semiconductor integrated circuitaccording to claim 1, wherein said substrate is an insulator, and saidfirst isolation region is in contact with said substrate.
 3. Asemiconductor integrated circuit according to claim 1, wherein saidsubstrate has a semiconductor layer formed on a semiconductor substratevia a first insulator and said first isolation region is in contact withsaid first insulator.
 4. A semiconductor integrated circuit according toclaim 1, wherein said first isolation region is comprised of a firstinsulation film, a third gate electrode, and a second insulation film.5. A semiconductor integrated circuit comprising:a substrate having asemiconductor layer on at least a first main surface thereof; a firstregion of a first type of conductivity formed in said semiconductorlayer; a second region of a second type of conductivity formed in saidsemiconductor layer; a first semiconductor proruding pole-like region ofthe second type of conductivity that is so provided as to come intocontact, with at least a portion thereof, with said first region, and asecond semiconductor protruding pole-like region of the first type ofconductivity that is so provided as to come into contact, with at leasta portion thereof, with said second region, wherein the first and secondsemiconductor protruding pole-like regions are provided as a mesa; athird region of the first type of conductivity provided in said firstsemiconductor protruding pole-like region; a fourth region of the secondtype of conductivity provided in said second semiconductor protrudingpole-like region; a first gate electrode formed on said firstsemiconductor protruding pole-like region via first insulating film; anda second gate elecrode formed on said second semiconductor protrudingpole-like region via a second insulating film; and a first isolationregion provided between said first semiconductor protruding pole-likeregion and said second semiconductor proruding pole-like region, whereinsaid substrate is an insulator, and said first isolation region is incontact with said substrate.